| PART |
Description |
Maker |
| ISPLSI2064VL-100LB100 ISPLSI2064VL-100LJ44 ISPLSI2 |
2.5V In-System Programmable SuperFAST?High Density PLD
2.5V In-System Programmable SuperFAST?/a> High Density PLD
2.5V In-System Programmable SuperFAST⑩ High Density PLD
2.5V In-System Programmable SuperFAST High Density PLD
Turns Counting Dial; Number of Turns:10; Knob/Dial Style:Round Skirted With Indicator Line; Body Material:Aluminum; Shaft Size:1/4; Color:Satin RoHS Compliant: Yes EE PLD, 10 ns, PQFP100
2.5V In-System Programmable SuperFASTHigh Density PLD EE PLD, 10 ns, PQFP100
2.5VIn-SystemProgrammableSuperFASTHighDensityPLD
|
LATTICE[Lattice Semiconductor]
Lattice Semiconductor Corporation
Lattice Semiconductor, Corp.
|
| ISPLSI1032EA-170LT100 ISPLSI1032EA-200LT100 1032EA |
60 MHz in-system prommable high density PLD
170 MHz in-system prommable high density PLD
125 MHz in-system prommable high density PLD
100 MHz in-system prommable high density PLD
Shielded Paired Cable; Number of Conductors:8; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyethylene; Shielding Material:Aluminum Foil/Polyester Tape/Tinned Copper Braid; Number of Pairs:4 RoHS Compliant: Yes
In-System Programmable High Density PLD 在系统可编程高密度可编程逻辑器件
|
LATTICE[Lattice Semiconductor]
Lattice Semiconductor Corporation
Lattice Semiconductor, Corp.
|
| ISPLSI2064VE ISPLSI2064VE-100LB100 ISPLSI2064VE-10 |
3.3V In-System Programmable High Density SuperFAST?PLD
3.3VIn-SystemProgrammableHighDensitySuperFASTPLD
3.3V In-System Programmable High Density SuperFASTPLD EE PLD, 7 ns, PQFP44
CRYSTAL 16.0 MHZ 20PF SMD EE PLD, 13 ns, PQFP100
CRYSTAL 20.0 MHZ 20PF SMD
RES 180K-OHM 1% 0.063W 200PPM THK-FILM SMD-0402 TR-7-PA2MM
3.3V In-System Programmable High Density SuperFAST PLD
3.3V In-System Programmable High Density SuperFAST⑩ PLD
3.3V In-System Programmable High Density SuperFAST?/a> PLD
280 MHz 3.3V in-system prommable superFAST high density PLD
|
Lattice Semiconductor, Corp.
Lattice Semiconductor Corporation
LATTICE[Lattice Semiconductor]
|
| ISPLSI2096VE-100LT128 ISPLSI2096VE-135LT128 ISPLSI |
3.3V In-System Programmable SuperFAST?/a> High Density PLD
CRYSTAL 24.0 MHZ 20PF SMD
3.3V In-System Programmable SuperFASTHigh Density PLD
3.3V In-System Programmable SuperFAST High Density PLD
3.3V In-System Programmable SuperFAST⑩ High Density PLD
3.3VIn-SystemProgrammableSuperFASTHighDensityPLD
|
Lattice Semiconductor Corporation
LATTICE[Lattice Semiconductor]
|
| ISPLSI1024 ISPLSI1024EA-200LT100 1024EA ISPLSI1024 |
200 MHz in-system prommable high density PLD
Shielded Paired Cable; Number of Conductors:8; Conductor Size AWG:28; No. Strands x Strand Size:7 x 36; Jacket Material:Polyethylene; Number of Pairs:4; Features:Alumunium Foil Polyester/Tinned Copper Braid; Impedance:120ohm RoHS Compliant: Yes
In-System Programmable High Density PLD
100 MHz in-system prommable high density PLD
|
Lattice Semiconductor Corporation
LATTICE[Lattice Semiconductor]
http://
|
| QL2009 QL2009-0PB256C QL2009-0PB256I QL2009-0PF144 |
3.3V and 5.0V pASIC 2 FPGA combining speed, density, low cost and flexibility.
3.3V and 5.0V pASIC? 2 FPGA Combining Speed Density Low Cost and Flexibility
3.3V and 5.0V pASICò 2 FPGA
3.3V and 5.0V pASIC? 2 FPGA Combining Speed, Density, Low Cost and Flexibility
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility(高速，高可用密度，低成本、可适应性强.3V.0V pASIC 2系列场可编程逻辑器件)
PT 6C 6#20 PIN RECP
PT 8C 8#20 PIN RECP
3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility 3.3V.0V帕希奇？ 2 FPGA的结合速度，密度，低成本和灵活
|
List of Unclassifed Manufacturers
ETC[ETC]
Electronic Theatre Controls, Inc.
QuickLogic Corp.
|
| ISPLSI2192VL-100LB144 ISPLSI2192VL-100LT128 ISPLSI |
2.5V In-System Programmable SuperFAST High Density PLD
TRIAC STANDARD 12A 400V TO-220AB
2.5V In-System Programmable SuperFASTHigh Density PLD
|
Lattice Semiconductor Corporation
|
| ISPLSI2032E ISPLSI2032E-110LJ44 ISPLSI2032E-110LT4 |
In-SystemProgrammableSuperFASTHighDensityPLD
In-System Programmable SuperFASTHigh Density PLD
In-System Programmable SuperFAST High Density PLD 在系统可编程超快高密度可编程逻辑器件
|
Lattice Semiconductor Corporation
Lattice Semiconductor, Corp.
|
| PC816CD PC616C PC816BD PC816AB PC816AC PC846 PC816 |
Hgh Collector-emitter Voltage, Hgh Density Mounting Type Photocoupler
Hgh -w=der Vtige Hgh Density Mounting Type Photocoupler
Hgh -w=der Vtige/ Hgh Density Mounting Type Photocoupler
High Collector-Emitter Voltage High Density Mounting Type Photocoupler(259.15 k)
Hgh -w=der Vtige, Hgh Density Mounting Type Photocoupler 杭州到瓦特\u003dVtige，生长激素密度安装类型光电耦合
|
SHARP[Sharp Electrionic Components]
Sharp Corporation
Sharp, Corp.
|
| ISPLSI2192VE100LB144 ISPLSI2192VE100LB144I ISPLSI2 |
3.3V In-System Programmable SuperFAST?High Density PLD
3.3V In-System Programmable SuperFAST?/a> High Density PLD
3.3V In-System Programmable SuperFAST High Density PLD
3.3V In-System Programmable SuperFAST垄芒 High Density PLD
3.3V In-System Programmable SuperFAST⑩ High Density PLD
EE PLD, 13 ns, PQFP128
|
LATTICE SEMICONDUCTOR CORP
|
| DK50-1.0 DK50-1.0M DK44-1.0 DK44-1.0M DK60-1.0 DK6 |
1.0mm High Density FLEX (300V, 105隆?C)
1.0mm High Density FLEX (300V, 105掳C)
1.0mm High Density FLEX (300V, 105°C)
|
Yamaichi Electronics Co., Ltd.
http://
|
| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
